(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly it pertains to a transistor which provides high speed operation without sacrificing the effective characteristics of the whole device which incorporates such transistors, and it further concerns an integrated circuit structure using these transistors.
(b) Description of the Prior Art
In conventional integrated logic circuits, known bipolar transistors have been adopted, in spite of their large power dissipation, due to the characteristics of these bipolar transistors such as, for example, large transconductance, high-speed operation and large driving ability. For these reasons, bipolar transistors have been used in, for example, those computing sections of a semiconductor integrated circuit which are required to operate at high speed, and also as elements constituting interface portions between integrated circuits which require a large driving ability.
Semiconductor devices or integrated circuits which employ known such bipolar transistors as stated above, include the so-called emitter-coupled logic (ECL), emitter-follower logic (EEL), non-threshold logic (NTL), integrated injection logic (IIL), diode transistor logic (DTL), a resistor transistor logic (RTL), dynamic random access memory (D-RAM), static random access memory (S-RAM), read-only memory (ROM) and like devices.
FIG. 1A shows a diagrammatic cross-sectional view of a semiconductor device formed with known high-speed bipolar transistors utilizing a stepped electrode transistor (SET) structure. Because of this SET structure, the distance between an emitter region 5 and a base region 4 can be greatly reduced, and thus the area which is occupied by the base region 4 and the area occupied by the collector region 2 can both be reduced substantially. Accordingly, so-called base resistance, the base-collector capacitance and the collector-substrate capacitance can each be reduced, thereby the operation speed of this semiconducted device can increase. This semiconductor device comprises: a substrate 1 constituted by a p type region, an embedded collector region 2 constituted by an n.sup.+ type region having an impurity concentration of about 10.sup.18 to 10.sup.20 cm.sup.-3, an n type region 3 having an impurity concentration of about 10.sup.14 to 10.sup.17 cm.sup.-3, a base region 4 constituted by a p type region having an impurity concentration of about 10.sup.17 to 10.sup.18 cm.sup.-3, an emitter region 5 constituted by an n.sup.+ type region having an impurity concentration of about 10.sup.20 to 10.sup.21 cm.sup.-3, an insulator region 6, a doped polycrystalline silicon region 7, and electrodes 2', 4', 4" and 5'. In this known semiconductor device, the isolation of each transistors is accomplished by the p type region. This isolation may be carried out by relying on the IOP (Isolated by Oxide and Polycrystalline Silicon) technique which employs polycrystalline silicon, or by relying on the Isoplanar Isolation technique which employs an insulating material such as silicon oxide (SiO.sub.2). This kind of bipolar transistors of an SET type can be applied to a non-threshold logic (NTL) circuit of FIG. 2 which is said to be able to provide the highest operation speed at the present state of techniques.
FIG. 2 shows a diagrammatic circuit of an non-threshold logic (NTL) circuit, to which the conventional semiconductor device of FIG. 1 is applicable. According to the experiment conducted by the inventor by incorporating the above-said bipolar transistors in non-threshold logic (NTL) circuit to form a 15-stage ring oscillator, there has been measured a transfer delay time of 85 picoseconds (refer to Technical Digest of ISSCC 77, FAM 16.1, T. SAKAI et al "A 100 Pico-Second Bipolar Logic" pp. 196-197). This high speed operation is attributable to the fact that the base resistance and the base-collector capacitance are reduced. However, in such a high speed semiconductor device capable of making a high speed, the electric characteristics of the region located between the collector region 2 and the substrate 1 present an important problem that must be solved.
By referring to FIGS. 1A and 2, the emitter potential V.sub.EE of this semiconductor device is supplied through a resistor R.sub.2 and a parallel capacitor C.sub.1 to the emitters of two bipolar transistors, respectively. This emitter potential V.sub.EE is usually set at about -1.1 V.
The substrate 1, which in this example is of p type, of the semiconductor device in FIG. 2 is usually kept at the ground potential. The impurity concentration of this substrate 1 is selected to be low, for example about 10.sup.14 -10.sup.16 cm.sup.-3, for the purpose of decreasing the capacitance between the collector region 2 and the substrate 1. The lower the impurity concentration of the p type substrate is, the smaller the capacitance between the collector region 2 and the substrate 1 becomes. Furthermore, the width of the depletion layer, which in this example extends from the collector region 2 toward the substrate 1, will vary in accordance with the changes in the voltage which is applied to the collector region 2. However, if the impurity concentration of the substrate 1 is lowered, the variations of the width of this depletion layer growing between the collector region 2 and the substrate 1 will become unable to quickly respond to quick changes in the voltage which is applied to the collector region 2. This time delay which occurs in the variation of the width of the depletion layer will bring about drawbacks and inconveniences which will be discussed below. In the event that such time delay exists, it may be viewed as if a conductance has appeared between the collector region 2 and the substrate 1 in parallel with the capacitance between the collector region 2 and the substrate 1 during the high speed operation, i.e. against quick changes in the collector voltage, and this brings about a degradation of the characteristics of said transistor in its high speed operation (refer to Semiconductor Electronics Vol. 13, Chapter 4, Takahiro OHMI, "TUNNETT" Microwave and Millimeter-Wave Oscillation). Therefore, if the impurity concentration of the substrate is lowered in an effort to reduce the collector-substrate capacitance, an undesirable increase in the share of contribution by the conductance will result. On the other hand, an effort to reduce this contribution shared by the conductance by an increase in the impurity concentration of the substrate will undesirably result in an increase in the collector-substrate capacitance which, in turn, deteriorates the frequency characteristic of the transistor.
The occurrence of such deterioration in the frequency characteristic of the transistor is not limited in planar bipolar transistors, but will develop in all those transistors, such as static induction transistors (SIT), junction field effect transistors as well as MOS field effect transistors, which have an embedded electrode and which are such that the potential of this embedded electrode is adapted to vary in the operative state of these transistors.
Furthermore, the deteriorating behavior of the depletion layer of a semiconductor device discussed above will be described in further detail hereinbelow by referring to FIGS. 1B and 1C.
Usually, an embedded electrode region is formed in a substrate 1 having a conductivity type opposite to the conductivity type of said embedded region, and forms a p-n junction therebetween. The potentials of the substrate 1 and the embedded electrode 2 are so selected that said p-n junction are reversely biased in the operative state of the semiconductor device. The potential of the substrate 1 is kept constant. However, the potential of the embedded electrode 2 will vary in the operative state. For example, in case of a transistor which is used especially as a transistor intended for switching operation, the potential of the embedded electrode of such transistor will vary between two predetermined potential values. If the potential of the embedded electrode 2 changes slowly or gently, the width of the depletion layer growing from the embedded electrode 2 toward the substrate 1 will change immediately in response to such slow or gentle potential change of the embedded region. However, if the speed of the potential change of the embedded region, or in other words, the switching speed for example, becomes greater, the variation speed of the width of the depletion layer will cease to follow the quick potential changes of the embedded region. As a consequence, the region between the embedded electrode region 2 and the substrate 1 will no longer be equivalent to a mere capacitance due to the depletion layer contained between the region 2 and the substrate 1, but rather will be equivalent to the combination of a conductance has become to be in parallel to the capacitance. Simple models of such instance will be shown hereunder by utilizing small signal approximation and with respect to structure and dimension of semiconductor device.
FIGS. 1B and 1C are a diagrammatic structure of a bipolar transistor and its equivalent circuit, respectively. The semiconductor device of FIG. 1B comprises an n.sup.+ type embedded electrode region 2 having an area of 1.75.times.10.sup.-5 cm.sup.2 (which generally corresponds to a collector area of a bipolar transistor relying on the Isoplanar technique), a p type substrate having a thickness of 300 .mu.m, and an electrode region 11 provided on the substrate 1. Furthermore, let us assume that a reverse bias of 1 V is applied between the n.sup.+ type embedded electrode region 2 and the electrode region 11 of the substrate 1. In FIG. 1C, this circuit comprises a capacitance C which is produced by the depletion layer and a resistance r formed by an electrically neutral region in the substrate 1. In this structure, when the impurity concentration N.sub.D of the substrate 1 is selected to be 1.times.10.sup.14 cm.sup.-3, the capacitance C and the resistance r will become 0.038 pF (pico-Farad) and 11 k.OMEGA. (kilo-ohms), respectively. Also, in case the impurity concentration is selected to be 1.times.10.sup.15 cm.sup.-3, the capacitance C and the resistance r will be 0.12 pF and 1.1 k.OMEGA., respectively. In these instances, the time constant rc will be 0.41 nano-second and 1.13 nano-second, respectively.
If it is intended that this semiconductor device effect switching operation at a speed less than 1 nano-second, i.e. is a so-called sub-nano-second device, the state of this semiconductor device will become equivalent to the state as if there is connected a resistance of 11 k.OMEGA. or 1.1 k.OMEGA., depending on the above-mentioned two instances (which, as conductance, corresponds to 93 micro-mho (.mu. ) or 930 .mu. ) between the embedded electrode region 2 and the substrate 1.
On the other hand, since the current which flows through a such transistor is typically of the order of several hundred micro-amperes, the resistance of the transistor will be approximately several kilo-ohms. This means that the resistance which appears between the embedded electrode region 2 and the substrate 1 is almost identical in magnitude to that of the transistor itself. Therefore, such condition is as if the transistor contains a very large load within itself. As a result the gain of the transistor will decrease markedly, and consequently its operation speed will drop sharply.